FPGA RTL Design Engineer at Megh Computing
Bangalore, IN

Megh Computing is looking for a FPGA RTL Engineer to develop infrastructure/algorithms for Realtime Data Analytics Solutions on Intel PAC Card using Intel OPAE stack. You must be a self-motivated, team player who is excited about working on leading edge technologies to solve customer’s problems and driving the success of the company.

Responsibilities and Duties

Primary responsibilities include:

  • Develop FPGA RTL infrastructure to allow offload on compute intensive algorithms on to FPGA.
  • Redesign/remap Big Data/DL algorithm to FPGA.
  • Design and implement unit tests for the solution within the test framework.
  • Work with software architects to design and implement applications:
    • With reviews at each stage to ensure integration into the larger system
    • With an eye to future maintenance
    • With simplicity and clarity

Qualifications and Experience

The following qualifications are required:

  • BS/MS with 4-10 years relevant experience.
  • Degree programs in CE, EE or similar technical field.
  • Development experience with RTL/HLS on FPGA/ASIC.
  • Experience in developing using VHDL, Verilog and System Verilog languages.
  • Knowledge of Linux User and/or Kernel Mode development.

The following qualifications are highly desirable (a successful candidate need not possess all of these qualifications, although the more the better):

  • Experience with mapping various workloads to CPUs and accelerators, including implementing algorithms on FPGAs.
  • Prior experience working with Heterogenous (FPGA, GPGPU) hardware systems.
  • Strong technical and problem solving skills.
  • Strong written and verbal communications skills.
  • Ability to define and execute tasks with limited direction.
  • Experience in test or validation application development.